Semiconductor integrated circuits frequently require internal capacitors for various circuit applications. These circuit applications include linear capacitor arrays for analog circuits, resistor-capacitor delay stages, and decoupling capacitors for power supplies and other low frequency decoupling. These capacitors are frequently fabricated as parallel plate capacitors with a silicon dioxide dielectric. Referring to FIG. 1, the capacitance of such parallel plate capacitors is given by equation (1).
                    C        =                              A            ⁢                                                  ⁢                          ɛ              o                        ⁢                          ɛ              r                                d                                    (        1        )            Here, A is the area of the capacitor and d is the dielectric thickness. The permittivity of free space ∈o is 8.854e-14 farads/cm. The relative permittivity or dielectric constant ∈r is a dimensionless property of the dielectric material. The relative permittivity for silicon dioxide is 3.9. Capacitance C for a parallel plate capacitor as in FIG. 1, therefore, is determined by geometrical parameters A and d, since ∈o is fixed and ∈r is determined by the silicon dioxide dielectric. Thus, capacitance C is proportional to area A and inversely proportional to dielectric thickness d.
For many applications, the parallel plate capacitor of FIG. 1 is formed with a thermally grown silicon dioxide dielectric 106. A lower plate 108 is formed by a crystalline silicon substrate and electrically connected to terminal C− 102. An upper plate 104 is formed by a polycrystalline silicon or metal electrode and electrically connected to terminal C+ 100. The crystalline silicon substrate is often highly doped with N-type or P-type impurities to reduce resistance. A good thermally grown silicon dioxide dielectric can typically withstand a maximum electric field of up to 10 MV/cm or 1 V/nm. Thus, thermally grown silicon dioxide dielectric is often preferred for high voltage applications. By way of comparison, a good deposited silicon dioxide dielectric may only tolerate a maximum electric field of up to 3 MV/cm or 0.3 V/nm. This deposited silicon dioxide dielectric, however, may be advantageously formed between metal or polycrystalline silicon plates. For either thermally grown or deposited silicon dioxide, however, operating voltages must be limited so that the maximum electric field remains well below the dielectric rupture threshold to avoid dielectric wear out over time. A minimum dielectric thickness d, therefore, is limited by circuit operating voltages. Any increase in capacitance C for a parallel plate capacitor having a silicon dioxide dielectric must be achieved by an increase in area A.
Alternative dielectrics are used to increase capacitance of parallel plate capacitors. Silicon nitride, having a dielectric constant of 9, is typically used as a composite dielectric with silicon dioxide to increase effective capacitance per unit area. For example, a composite dielectric stack comprising a silicon nitride layer formed between silicon dioxide layers is often used for dynamic random access memory cell storage capacitors. For the same dielectric thickness d, therefore, a memory cell storage capacitor with a silicon nitride dielectric will advantageously realize a capacitance equivalent to that of a silicon dioxide dielectric capacitor in 43% of the area.
Ferroelectric materials exhibit a substantially greater dielectric constant than either silicon nitride or silicon dioxide. The term ferroelectric is something of a misnomer, since present ferroelectric capacitors contain no ferrous material. Typical ferroelectric capacitors include a dielectric of ferroelectric material formed between two closely-spaced conducting plates. One well-established family of ferroelectric materials known as perovskites has a general formula ABO3. This family includes Lead Zirconate Titanate (PZT) having a formula Pb(ZrxTi1−x)O3. This material is a dielectric with a desirable characteristic that a suitable electric field will displace a central atom of the lattice. This displaced central atom, either Titanium or Zirconium, remains displaced after the electric field is removed, thereby storing a net charge. A typical PZT dielectric constant is about 500. Another family of ferroelectric materials is Strontium Bismuth Titanate (SBT) having a formula SbBi2Ta2O9. A typical SBT dielectric constant is about 200. However, state-of-the-art fabrication of both ferroelectric materials often results in a high defect density. The high defect density produces local areas of high leakage current proximate each defect. Thus, large area capacitors fabricated with these dielectrics may suffer from prohibitively high leakage.
Referring to FIG. 2, there is a hysteresis curve of a typical ferroelectric capacitor as in FIG. 1. The hysteresis curve includes net charge Q or polarization along the vertical axis and voltage V along the horizontal axis. By convention, the polarity of cell voltage is defined as shown in FIG. 1. A “0” state, therefore, is characterized by a positive voltage at terminal C− 102 with respect to terminal C+ 100. A “1” state is characterized by a negative voltage at terminal C− 102 with respect to terminal C+ 100. A “0” state is achieved by applying a voltage Vmax across the ferroelectric capacitor. This stores a saturation charge Qs in the ferroelectric capacitor. The ferroelectric capacitor, however, includes a linear component in parallel with a switching component. When the electric field is removed, therefore, the linear component discharges and only the residual charge Qr remains in the switching component. The “0” is transformed to a “1” state by applying −Vmax to the ferroelectric capacitor. This charges the linear and switching components of the ferroelectric capacitor to a saturation charge of −Qs. The stored charge reverts to −Qr when the electric field is removed. Finally, coercive points VC and −VC are minimum voltages on the hysteresis curve that will degrade a stored data state. For example, application of VC across a ferroelectric capacitor will degrade a “1” state even though it is not sufficient to produce a “0” state.